1. Field of the Invention
The present invention relates to a method for manufacturing a transistor, specifically a thin film transistor, having an LDD region, and further relates to a semiconductor device using the manufacturing method.
2. Related Art
A semiconductor display device formed by using an inexpensive glass substrate cannot easily be miniaturized since a peripheral area (frame area) of a pixel portion required for mounting occupies more area in a substrate as resolution becomes higher. Thus, it is considered that there is a limitation on a method for mounting an integrated circuit formed by using a single crystalline silicon wafer on a glass substrate. Therefore, a technique for integrally forming an integrated circuit including a driver circuit over a glass substrate provided with a pixel portion, that is referred to as System On Panel, is now focused on.
However, an integrated circuit formed over a glass substrate has lower degree of integration than that of an integrated circuit formed over a single crystalline silicon wafer. Therefore, it is an important object to miniaturize a semiconductor element on practical application. According to miniaturization of a semiconductor element, an integrated circuit formed over a glass substrate can highly be integrated, thereby promoting miniaturization, weight reduction, further, low power consumption, and speedup of a semiconductor display device. In addition, according to miniaturization of a semiconductor element as well as an integrated circuit, high definition can be realized also in a pixel portion.
A semiconductor display device provided with a thin film transistor (TFT) using an amorphous semiconductor film in a pixel portion has the advantage of having high productivity and low cost. However, the TFT using an amorphous semiconductor film has the disadvantage of having low mobility. Therefore, it is considered that a thin film transistor using an amorphous semiconductor film is unsuitable for a driver circuit that required high-speed operation such as a scanning line driver circuit for selecting a pixel or a signal line driver circuit for supplying a video signal to the selected pixel. Thus, a mode of manufacturing an IC chip in which a driver circuit is included by using a single crystalline silicon wafer and of mounting the IC chip on the periphery of a pixel portion by TAB (Tape Automated bonding) or COG (Chip on Glass) is generally adopted.
However, a unit cost of a silicon wafer is higher than that of a glass substrate, and a silicon wafer is not suitable for providing an inexpensive IC chip. The advantage of a low cost that is a characteristic of a semiconductor display device using an amorphous semiconductor film cannot fully be utilized. The sizes of silicon wafers that are comparatively a lot on the market are approximately not more than 12 inches in diameter. Although more than 12 inches sized silicon wafers are also on the market, a cost per unit area further increases as its size increases. Consequently, costs have to be sacrificed in order to increase throughput by increasing the number of IC chips obtained from one substrate.
Thus, a technique of forming a driver circuit over a glass substrate, dividing into strips, and mounting on a substrate over which a pixel portion is formed is disclosed in the following references (Reference 1: Japanese Patent Application Laid-Open No. 7-014880, and Reference 2: Japanese Patent Application Laid-Open No. 11-160734).
As disclosed in References 1 and 2, an incidence rate of a defect in a contact portion of a terminal, caused by a difference of a thermal expansion coefficient can be decreased by using a substrate made of the same material as a substrate over which a pixel portion is formed (hereinafter, referred to as an element substrate), forming a driver circuit, and mounting on the element substrate. Accordingly, a yield can be increased. In addition, a cost of a semiconductor display device as a whole can be reduced by forming a driver circuit over a glass substrate.
Meanwhile, a semiconductor display device cannot easily be miniaturized since a peripheral area (frame area) of a pixel portion required for mounting occupies more area in a substrate as resolution of a pixel portion becomes higher. Therefore, an IC chip mounted on a substrate over which a pixel portion is formed is preferably smaller. However, an integrated circuit formed over a glass substrate has lower degree of integration than that of an integrated circuit formed over a single crystalline silicon wafer. Therefore, on promoting miniaturization of a semiconductor display device and high integration of an integrated circuit, it is an important object to miniaturize a semiconductor element formed over a glass substrate. When an integrated circuit formed over a glass substrate can highly be integrated according to miniaturization of a semiconductor element, miniaturization, weight reduction, further, low power consumption, and speedup of a semiconductor display device can be advanced.
However, miniaturization of a TFT that is one of semiconductor elements involves a problem of decline in reliability due to a hot carrier effect. Therefore, an LDD (Lightly Doped Drain) structure is adopted as a means of controlling a hot carrier effect. The LDD structure is a structure in which an LDD region having a lower impurity concentration than that of a source/drain region is provided between the source/drain region and a channel formation region. Particularly, it is known that in the case of having a structure in which an LDD region is overlapped with a gate electrode with a gate insulating film therebetween (GOLD structure, Gate Overlapped Lightly Doped Drain structure), a hot carrier effect can efficiently be prevented by relaxation of a high electric field in the vicinity of a drain and reliability can be improved. In this specification, a region in which an LDD region is overlapped with a gate electrode with a gate insulating film therebetween is referred to as an Lov region and a region in which an LDD region is not overlapped with a gate electrode is referred to as an Loff region.
It is disclosed in the following reference that deterioration of a transistor can be prevented by employing a GOLD structure (Reference 3: Japanese Patent Application Laid-Open No. 8-153875).
A TFT having an Loff region tends to be able to reduce more off current than a TFT having an Lov region. Therefore, a TFT having an Loff region is suitably used for a switching element of a pixel in which reduction of an off current is regarded as more important than high-speed drive. Meanwhile, a TFT having an Lov region can be driven at higher speed than a TFT having an Loff region. Specifically, switching can be performed at higher speed. A TFT having an Lov region is suitably used for a driver circuit since operating frequency is higher than that of a pixel portion and high-speed drive is regarded as more important than reduction of an off current. It is preferable that a TFT having an Loff region and a TFT having an Lov region are appropriately used according to characteristics required for a circuit element.
Several methods have been proposed for manufacturing a TFT having an Lov region, and one of them is to obliquely implant ions using a gate electrode as a mask. According to the above method, a dopant (impurity) can be added by an ion implantation method to a region overlapped with a gate electrode with a gate insulating film therebetween, without using a resist mask and with the number of steps reduced.
However, in order to form an Lov region on both a source region side and a drain region side, it is necessary to perform ion implantation twice from a different implantation direction. This can be a factor of preventing a throughput in a step of ion implantation from improving. In addition, there is a method (tilt rotation) for obliquely and uniformly implanting ions by rotating a substrate; however, according to this method, rotation of a substrate need to precisely be controlled and a large-scale apparatus for performing ion implantation is required. Particularly, the method is not suitable for a large substrate, and becomes a factor in preventing throughput from improving.
In addition, according to the above method, there is a problem that a TFT having an Lov region and a TFT having an Loff region cannot separately be formed over one substrate. According to the above method, a TFT having an Lov region and a TFT having an Loff region cannot separately be formed over one substrate in the case of integrating a pixel portion and a driver circuit by System On Panel. In addition, such a TFT without an LDD region that a source region and a drain region are in contact with a channel formation region and a TFT having an Lov region cannot separately be formed over one substrate.
A TFT having an Lov region and a TFT having an Loff region can separately be formed over one substrate by separately implanting a dopant using a resist mask. However, the number of resist masks and steps cannot be reduced, which becomes a factor of increasing a manufacturing cost. When a transistor having an offset gate structure, a transistor in which a source region and a drain region are in contact with a channel formation region, and the like as well as a TFT having an Loff region are intended to separately be formed over one substrate, the number of resist masks and steps cannot be reduced, which becomes a factor of increasing a manufacturing cost.